In conventional Ethernet controller implementations, a buffer pointer that defines an address in memory where a received frame is to be stored is typically defined within a frame descriptor produced by software executing on, for example, a central processing core. Upon receipt of a datagram comprising a frame of data, the Ethernet controller obtains the next frame descriptor for the appropriate ingress descriptor queue comprising the buffer pointer for the received frame, and the frame is written to memory at the address defined by the buffer pointer. The frame descriptor is then added to the appropriate descriptor queue. Such an approach works sufficiently well for most applications when there is only a single ingress descriptor queue.
However, if there are multiple ingress descriptor queues, and the Ethernet controller is required to parse the received data frame to enable a specific ingress descriptor queue to be determined, it is necessary to wait until the entire data frame has been received before the appropriate descriptor queue can be determined. For example, a frame is not validated until the Cyclic Redundancy Check (CRC) has been performed, and frames that fail the CRC may be required to be assigned to a “default queue” for frames that fail the CRC. As a result, a complete received frame is required to be stored within the Ethernet controller before the appropriate ingress descriptor queue can be determined, and thus before the next frame descriptor therefor can be obtained comprising the buffer point defining an address in memory where the received frame is to be stored. Only then can the received frame be written to memory, and internal memory of the Ethernet controller freed up for subsequently received frames. As such, the internal memory of the Ethernet controller has to be such that there is enough space to store incoming frames while the current frame is transferred to its buffer(s).
This need to store complete received frames increases the internal memory requirements of the Ethernet controller, adding undesirable power consumption and cost to the Ethernet controller hardware.